A precision 0.72 V sub-bandgap reference with 5.02 ppm/°C TC and optimized line and PSR characteristics

• A 0.72V sub-bandgap reference (Sub-BGR) circuit is presented using quadratic temperature compensation for high thermal stability. • The proposed architecture achieves an ultra-low Temperature Coefficient (TC) of 5.02 ppm/°C, showing a 58.7% to 78.6% improvement over conventional designs. • Subthreshold MOSFET-based curvature compensation effectively cancels second-order non-linearities in the base-emitter voltage. • Achieves enhanced Power Supply Rejection Ratio (PSRR) of −84.93 dB, outperforming earlier BGR designs. • Demonstrates excellent line regulation with a mean of 723 µV and a low standard deviation of 132 µV, ensuring robust operation under supply variations. • Designed and simulated in 32nm CMOS process using Synopsys Custom Compiler and validated across PVT corners and Monte Carlo analysis. • Suitable for low-power, high-precision analog and mixed-signal applications, including IoT, biomedical, and high-speed VLSI systems. In this work, a high-accuracy Bandgap Reference (BGR) circuit is proposed that incorporates second-order temperature compensation for improved thermal stability. The traditional BGR design relies on first-order compensation by balancing the temperature-dependent behavior of semiconductor devices. Since the base-emitter voltage exhibits nonlinear temperature behavior, first-order correction alone cannot fully eliminate curvature. As part of the proposed design, transistors operating in the subthreshold region are used to generate an additional compensation term, enabling precise correction of second-order temperature effects. In terms of Power Supply Rejection Ratio (PSRR), Temperature Coefficient (TC) and Line Regulation, the proposed sub-BGR is compared with sub-BGR and sub-BGR with Subthreshold MOSFET Curvature Compensation (sub-BGR-2-CC). BGRs with curvature correction architecture enhance thermal stability and decrease output reference voltage variation. Without curvature compensation, the proposed BGR's TC value is 9.2 ppm/°C. TC value can be reduced from 7.9 ppm/°C to 5.8 ppm/°C by introducing the curvature compensation mechanism, a 37% improvement in thermal stability. An implementation of the proposed BGR is simulated using the Synopsys Custom Compiler environment with 32-nm CMOS technology.