Interference-aware frequency-agile onboard processor using fine-grained multilevel analysis–synthesis filter-bank channelization

This paper proposes a spectrally optimized, multichannel filter-bank channelizer with time-multiplexed hardware reuse and block-based [Formula: see text] per-sample FFT complexity based on a unified framework for deep-space and satellite-onboard digital signal processing. This framework achieves fine-grained channelization using a single prototype filter with substantially reduced memory and computational overhead. The proposed approach derives all analysis and synthesis subband filters from a single prototype FIR filter using dyadic dilation and structured cascading. This eliminates the need for independently designed subfilters, achieves uniform channel spacing with consistent group delay, and reduces spectral distortion across all bands. A multi-objective cost-function-based prototype filter was obtained for the multilevel tree-structured uniform filter bank by minimizing transition-band energy, stop-band energy, and hardware complexity under QPSK recovery constraints. Strong channel isolation, a sharp roll-off, and reliable reconstruction at every level of the hierarchy are demonstrated by comprehensive simulation-based spectrum analysis. These channelizers are well-suited for onboard digital processors in next-generation satellite and deep-space missions. Simulation results demonstrate an average adjacent-channel isolation exceeding 98 dB (with a worst-case value of 79.6 dB) for a 64-channel 10 kHz frequency grid, while maintaining the QPSK error vector magnitude (EVM) below 10%. Fixed-point simulations and FPGA synthesis results confirm that the architecture maintains communication-relevant isolation (>60 dB worst-case) under practical finite word-length constraints, demonstrating realistic hardware feasibility.