Recent advances in rolled-up on-chip devices

Planar integrated-circuit architectures, optimized for processing features on two-dimensional wafers, have historically delivered rising density and performance. However, continued planar scaling is increasingly limited by leakage/short-channel effects, escalating power density and thermal constraints, while heterogeneous blocks (passives, logic, sensors, memory, and power) compete for chip area, restricting system-level functional density. Thin-film self-rolling offers a deterministic 3D assembly route that converts planar-fabricated nanomembranes into tubular architectures through strain relaxation after sacrificial-layer release. The resulting 3D microtubes enable drastic footprint reduction, tunable diameter and winding number, and new electrical/optical/magnetic coupling geometries, while retaining strong CMOS compatibility. In this review, we summarize leading fabrication strategies for rolled-up on-chip devices, contrasting external-force-assisted rolling with more controllable internal strain-gradient approaches and comparing wet versus dry release routes for integration yield and manufacturability. We then survey fundamental rolled-up components (capacitors, inductors/transformers, and resonators) and benchmark representative performance against state-of-the-art planar counterparts. Next, we review rolled-up sensors and active devices, spanning integrated FET microtubes, photodetectors, and magnetoresistance sensors, followed by information storage/processing concepts such as tubular magnetic domains and rolled-up racetrack memories. We further discuss rolled-up microenergy devices (supercapacitors and microbatteries) and outline key hurdles, such as ohmic loss, heat accumulation, and packaging, together with emerging mitigation strategies. Looking forward, co-integrating heterogeneous rolled-up building blocks into unified tubular circuits could provide a practical beyond-Moore pathway toward compact, multifunctional electronics. Continued advances in materials, wafer-scale yield, and 3D packaging will be pivotal for translating rolled-up architectures into impactful hardware for sensing, communication, and computing.