A Low‐Delay Contention‐Free Dual‐Edge‐Triggered Pulsed Flip‐Flop Based on Multiple‐Pulse

ABSTRACT Conventional dual‐edge‐triggered flip‐flops suffer from structural complexity and redundant switching issues, frequently leading to elevated power consumption and increased delay. To address this, we propose a low‐delay, low‐power, contention‐free dual‐edge multiple‐pulse flip‐flop (CFMPFF). The proposed circuit generates two single‐edge pulse signals, where one shortens the critical delay in the charging path and the other eliminates contention in the latch keeper. Simultaneously, it completely eradicates redundant switching activities in the two‐stage latch structure, achieving significant reductions in both power consumption and D‐to‐Q delay. Implemented in 28‐nm CMOS technology and simulated in HSPICE, performance evaluations against state‐of‐the‐art dual‐edge flip‐flops demonstrate that the proposed CFMPFF achieves D‐Q delay reductions ranging from 64.56% to 77.34%. Benefiting from co‐optimized power and delay characteristics, the CFMPFF achieves the lowest power‐delay product (PDP) among all compared designs, corresponding to a PDP reduction ranging from 56.16% to 86.05%. Furthermore, the design maintains robust operation under process, voltage, temperature (PVT) variations, while also delivering reliable performance at frequencies of up to 1 GHz, exhibiting lower D‐to‐Q delay and PDP characteristics compared with existing solutions.