Design Exploration of 3D Stacked Nanosheet FETs under Temperatureand Work Function Variation: Insights for 5-nm Nanoscale Device Integration

Introduction: Gate-All-Around (GAA) Nanosheet FETs (NSFETs) have emerged as promising candidates for sub-5 nm technology nodes due to their superior electrostatic control and scalability. This study provides an in-depth analysis of their DC performance, focusing on the effects of temperature and metal gate work function variations on device operation. Methods: Through numerical TCAD simulations, we explore critical DC metrics such as ON-state current, OFF-state current, threshold voltage, subthreshold slope, switching ratio, and Drain-Induced Barrier Lowering. The analysis extends over an operating temperature range from 275 °K to 450 °K and TiN metal gate work function values between 4.3 eV and 4.9 eV. Result: The results indicate a significant performance shift with increasing temperature. Ion drops by approximately 44.37%, while Ioff increases exponentially by nearly five orders of magnitude, leading to a significant 99.8% reduction in the Ion/Ioff ratio. Key figures of merit, such as SS, DIBL, and Vth, also exhibit strong thermal sensitivity. A temperature compensation point (TCP) is identified at VGS = 0.45 V and ID = 40.40 μA. Conversely, increasing Фm results in enhanced control over leakage and switching behavior. Results show that Ion decreases by 84.15%, while significantly improving the Ion/Ioff ratio. The Vth increases by 273%, with notable improvements in SS Ioff reduces by over six orders of magnitude, and DIBL. Discussion: Elevated temperature degrades device reliability by reducing Ion, exponentially increasing Ioff, and deteriorating SS, DIBL, and Vth. In contrast, optimizing the gate work function provides effective leakage suppression, improved switching behavior, and enhanced control over shortchannel effects. Conclusion: This investigation offers critical insights into thermal and electrostatic tuning of NSFETs, demonstrating that optimized gate work function selection can effectively mitigate temperature- induced performance degradation, making NSFETs promising candidates for future lowpower, high-performance digital applications.