Design Space Exploration for Approximate Circuits Based on Arithmetic Calculus Modeling

Approximate computing (AC) is a paradigm that introduces errors for reduced design metrics. AC has been recommended for implementation in error-resilient applications. Previously proposed AC implementations can be modified to generate new configurations and thus result in a large design space of AC. In this paper, we propose a design space exploration (DSE) approach for AC that drastically reduces the design space and finds an optimal configuration. A distinguishing feature of the proposed DSE is its theoretical nature for quality assessment instead of the traditionally used simulation based methods. Towards this goal, we propose a DSE approach based on mathematical modeling for approximate arithmetic designs, such as adders, multipliers, dividers, etc. Mathematically modeling the AC circuits facilitates the quality to be assessed using various error metrics while reducing the assessment time. The proposed approach has been applied to various arithmetic units, including an array multiplier, a multiply accumulate unit and a divider. The experimental results showed a quality assessment equivalent to the one obtained by the Monte-Carlo simulation, while offering a remarkable reduction in CPU time. Moreover, we observed a drastic reduction in the design space when applying the proposed DSE approach to AC hardware, i.e., approximate array multiplier.