Exploration of power reduction for Montgomery multiplication architectures for RSA

RSA (Rivest-Shamir-Adleman) is now being used in low-power devices to ensure secure communication without consuming much of the available limited energy on the device. This is achieved by using ASICs with power reduction techniques and also using efficient hardware algorithms. This work presents low-power Montgomery multiplication architectures for RSA implementation. Two different architectures of Montgomery multiplication which are radix-2 by Tenca-Koc and the very high radix (radix-2¹⁶) by Kelly-Harris are presented. Architectural changes are made to the radix-2 and radix-2¹⁶ Montgomery multiplication implementations to avoid race conditions and incorrect data flow. Also, the data flow in the carry save adders in the radix-2 architecture is rearranged to ensure that the design works for various operand lengths, number of processing elements and word sizes. Regulating the data flow in the high radix design has ensured that the design works for the condition that requires a FIFO. The aforementioned architectures suffer from high power consumption due to constant clock supply to the underlying processing elements that perform Montgomery multiplication. The aim of this work is to generate low-power Montgomery multipliers for radix-2 and radix-2¹⁶ designs using the clock gating methodology and then implement RSA modules using these multipliers to analyze power, performance, and area (PPA). The Montgomery multiplication and RSA architectures help to understand the trade-off between the designs in terms of PPA. The designs are simulated and synthesized for 256 and 1024 bits and have been evaluated for PPA using TSMC 28hpc+ 28 nm technology. Results indicate a 37% to 97% decrease in power for Montgomery multiplication architectures and a 15% to 51% decrease in power for RSA architectures. The results indicate a reduction in power over the original designs whilst having tradeoffs in choosing the number of words (w), number of processing elements (p) and operand size for implementation (n).