A 1-to-8 Programmable Clock Divider with a 50% Duty Cycle and Low Jitter for ADCs

In this paper, a programmable clock divider with a 50% duty cycle and low jitter for analog-to-digital converters (ADCs) is presented. The proposed divider, using a 180 nm CMOS process, can handle an input clock range from 40 MHz to 1 GHz. It supports integer division ratios from 1 to 8, with programmable phase shifting corresponding to each division ratio. To address the issue of the non-50% duty cycle with odd division ratios, this design combines edge-triggered and level-triggered flip-flops to simultaneously perform logical operations during the falling edge and high-level periods of the input clock, ensuring that the output clock maintains an accurate 50% duty cycle under all integer division ratios. Moreover, a clock-edge synthesis technique is adopted: three dividing timing signals are first generated to extract the pure edges of the input clock, which suppresses the excess jitter introduced by conventional multi-stage flip-flop chains. Simulation results show that, with a 1 GHz input clock, the RMS value of the jitter is less than 85.12 fs under the worst process corner, and the power consumption is less than 3.037 mW.