A 125- <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" altimg="si5.svg" display="inline" id="d1e679"> <mml:mi mathvariant="normal">μ</mml:mi> </mml:math> W 14-bit 5-MS/s pipelined-SAR ADC with linearity-enhanced bootstrapped switch and kT/C

A 14-bit 5MS/s pipelined-successive approximation register (SAR) analog-to-digital converter (ADC) is presented with high-linearity bootstrapped switches and kT/C noise cancellation. The proposed linearity-enhanced bootstrapped switch effectively isolates the critical signal path from the nonlinear parasitic capacitance and significantly improves the sampling spurious-free dynamic range (SFDR). By embedding a double-sampling noise cancellation mechanism into a two-stage dynamic residue amplifier to eliminate discrete-time kT/C noise, the proposed architecture overcomes the thermal noise limit and reduces the required sampling capacitance without incurring any static power penalty. To further reduce the overall power consumption and silicon area of the ADC, customized metal-oxide-metal (MOM) capacitors with low parasitic capacitance and compact layout are used in the 8-bit capacitive DAC (CDAC) within the second-stage sub-ADC. Fabricated in a 65-nm CMOS process, the prototype ADC occupies an active area of 0.123 mm 2 . Measurement results demonstrate a signal-to-noise-distortion ratio (SNDR) of 71.5 dB and an SFDR of 83 dB at the Nyquist input frequency. The total power consumption of the ADC is 125 μ W at 5 MS/s, yielding a Schreier figure of merit ( FoM S ) of 174.5 dB and a Walden figure of merit ( FoM W ) of 8.1 fJ/conversion-step.