11.3 A 500MS/s 12b Pipe-SAR ADC Using a Triple-Cascode FIA with Virtual Supply Extension
This paper presents a 28 nm CMOS 500 MS/s 12b three-stage pipeline SAR ADC based on a triple-cascode single-stage floating residue amplifier with virtual supply extension to improve its efficiency and linearity. The ADC achieves 63.4 dB SNDR and 81.0 dB SFDR at 240 MHz input across PVT variations, consuming 6.64 mW with on-chip digital calibrations and occupying 0.011 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>.
Authors
- Gabriele Bè (ORCID: https://orcid.org/0000-0002-4960-6877)
- Andrea L. Lacaita (ORCID: https://orcid.org/0000-0003-0315-514X)
- Luca Ricci (ORCID: https://orcid.org/0000-0003-2840-9695)
- Luca Bertulessi (ORCID: https://orcid.org/0000-0001-6167-6512)
- Andrea Bonfanti (ORCID: https://orcid.org/0000-0003-1974-2605)
- Salvatore Levantino (ORCID: https://orcid.org/0000-0003-0895-1700)
- Gabriele Zanoletti (ORCID: https://orcid.org/0000-0003-1179-2675)
- Alessia Ceroni
- Giacomo Tombolan
- Carlo Samori
- Michele Rocco
Institutions
- Politecnico di Milano (IT)
Publication Details
- Published
- 2026-02-15
- DOI
- https://doi.org/10.1109/isscc49663.2026.11409177
- Primary Topic
- Analog and Mixed-Signal Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 0.00