A 4042-PPI 10b 240Hz Digital-PWM CMOS Backplane for Micro-Led-on-Silicon Displays with a Shared, Unified Memory-in-Pixel Architecture

This paper presents a 10b 240Hz digital-PWM CMOS backplane for <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mu \text{LED}$</tex>-on-Silicon with a shared, unified memory-in-pixel structure. A unified D-FF chain (UDC) merges the in-pixel register, counter, and comparator into one reconfigurable unit. Hierarchical time-divided PWM (HTD-PWM) with shuffled rolling-shutter (SRS) time-multiplexes an LSB engine across <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1 \times 6$</tex> pixel clusters. Fabricated in 28 nm CMOS, the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$120 \times 120$</tex> backplane achieves 4042PPI and an 88% active-area, with DNL/INL of 0.9/7.1LSBs.