Demonstration of a subthreshold analog CMOS reservoir chip for temporal signal processing

Abstract We present a low-power analog CMOS reservoir computing chip that employs a simple ring topology for unidirectional nonlinear analog processing. Each node integrates a sample-and-hold circuit operating at 1 kHz, enabling compact and energy-efficient implementation in standard CMOS. The fabricated chip was evaluated on standard benchmarks, achieving a linear memory capacity of 13.4 and information processing capacities of 7.2 (second-order), 3.3 (third-order), and 1.2 (fourth-order). It also demonstrated competitive accuracy in both short- and long-term time-series forecasting tasks. Most notably, this performance was achieved with a power dissipation of only 20 μ W per core, highlighting the potential of analog CMOS reservoir computing for deployment in energy-constrained edge devices.