Avalanche stress in localized GaN epitaxial p–n diodes on 200 mm silicon substrates

In this study, we demonstrate avalanche breakdown in pseudo-vertical GaN power devices grown by selective area growth (SAG) on 200 mm Si substrates, offering a pathway to high performance with silicon fab compatibility and low cost compared to GaN-on-GaN devices. A 1.5 × 10 16 cm −3 silicon-doped GaN drift layer enabled the fabrication of an 805 V pseudo-vertical p–n diode. Device stability was initially evaluated by performing temperature-dependent reverse bias measurements (298–373 K) alongside DC stress conducted near the avalanche threshold. In the absence of dedicated edge termination, the peak electric field concentrates at the p–n junction sidewalls, triggering impact ionization and avalanche breakdown. Extended stress induces hard breakdown—driven by thermo-mechanical degradation—confirmed by post-failure SEM analysis. TCAD simulations corroborate the role of sidewall field enhancement in both avalanche initiation and failure mechanisms.