A novel FPGA-based time-to-digital converter featuring machine learning-aided self-calibration

• Proposes a novel FPGA-based Time-to-Digital Converter (TDC) using machine learning–aided self-calibration to overcome non-linearities that limit precision in conventional calibration methods. • Integrates placement and routing optimization with lightweight ML models (NN, DNN, CNN) trained on 300k+ raw TDC samples to correct residual non-linearities. • Demonstrates a hardware platform enabling real-time ML inference on FPGA via a multi-clock-domain architecture and Systolic Array accelerator. • Comprehensive comparison of ML models and traditional calibration approaches shows enhanced accuracy (13.6 ps standard deviation) and significantly reduced calibration time over prior TDC designs. Time-to-digital converters (TDCs) implemented on Field-Programmable Gate Arrays (FPGAs) encounter significant challenges in achieving high precision. Unlike Application-Specific Integrated Circuits, FPGA-based TDCs must depend on standard logic elements as delay units, with each contributing different propagation delays due to process variations and available routing resources. These inconsistencies introduce non-uniformities in time measurement, degrading accuracy and thus requiring extensive calibration. A second major challenge is adapting analog-based time measurement techniques to the inherently digital nature of FPGAs. This work proposes a novel approach that eliminates the lengthy, time-consuming manual calibration by combining placement and routing optimization with machine learning techniques. We propose an approach based on custom placement and routing to minimize disturbance, while remaining errors due to process variation are compensated exploiting machine learning-based correction models. The work proposes and evaluates three different Machine-Learning (ML) models to interpret raw TDC outputs. Exploiting ML, we achieve a high-precision time measurement system capable of addressing the disturbances and non-linearities intrinsic to FPGA-based TDCs. This approach significantly reduces design complexity, accelerates deployment, and enhances the precision of FPGA-based TDCs, making them more scalable and suitable for a broad range of applications. Experimental results on a Kintex UltraScale FPGA show that the proposed ML-aided TDC achieves a timing precision below 15 ps, improving the precision of a conventional encoder-based FPGA TDC by more than 10.5 × and reaching performance comparable to a state-of-the-art ASIC TDC.