A Framework for Automated Integration of High-Level Simulators in RISC-V SoCs

To achieve further performance and efficiency, System-on-Chip (SoC) designs increasingly rely on core customization or integration of application-specific hardware blocks. This requires extensive efforts during Design Space Exploration (DSE) of new hardware to achieve integration, correctness, and target performance. This is time-consuming and error-prone, hindering fast iterative hardware/software co-design. This paper presents a co-simulation framework which integrates arbitrary high-level simulators into Verilog-based SoC platforms, demonstrated on the RISC-V–based open-source X-HEEP SoC. Using inter-process communication we enable cycle-accurate lock-step co-simulation where high-level simulators of accelerators are exposed as memory-mapped peripherals to the RISC-V core. For experimental validation we re-implemented an existing peripheral of the X-HEEP SoC written in Register-Transfer Level (RTL) as an external simulator process, and observed that the cosimulated version maintains identical cycle-level behavior with a maximum wall-clock overhead of 11 %. This work enables fast DSEs of heterogeneous RISC-V–based SoCs.