A Novel Linear Feedback Shift Register-Driven Power Reduction Approach for Bist-Ready Very-Large-Scale Integrated Circuits

The testing of system on chip (SoC) components in very-large-scale integrated (VLSI) circuits presents significant challenges due to excessive power dissipation and data volume. The inherent complexity of VLSI circuits, which integrate numerous transistors on a single silicon substrate, increases fault likelihood, leading to large data volumes and longer test times. The conventional scan chain-based testing in design-for-testability (DFT) results in high switching activity and power consumption, especially during shift operations. Addressing low-power dissipation during testing is essential for chip durability, performance, cost and reliability. Otherwise, the chip may foresee power surges, voltage drops, hotspots, thermal stress, false timing failures and mismatches due to the reason that test power is always double that of the functional power. Thus, in this paper, a new architecture based on linear-feedback shift-register (LFSRs) driven architecture that is analogous to that of the traditional scan is proposed, to help diminish transition count, in turn decreasing power usage in the test mode. The architecture employs power gating and automatic test pattern generation (ATPG) filling methods in the contribution of ensuring the design is in a low power state that provides a high level of test coverage at the lowest switching activity. The experimentation is tested on ISCAS89 benchmarking circuits and on hyperconvoluted industrial designs with Cadence Genus and Modus tools. Scalability between small benchmark circuits and large industrial designs is confirmed by performance analysis of a wide range of circuit complexities. Experimental data demonstrates that the LFSR-based method showed a significant 1.34X decrease in the toggling activity, as well as an impressive 4–10 K decreasing pattern and an overall acceleration of the runtime of approximately 1–1.5[Formula: see text]h over the scan-based designs. Test coverage is enhanced 2.97–3.76 with the case of the static test, 6.03–7.51 with the case of the delay test and 0.41–0.59 with the case of scan tests. Test power recorded a decline of about 40–47 on industrial design, exhibiting its substantial findings on intricate designs.