Auto-Generation of VHDL Code for a Digital Circuit Sketch using Neural Networks

In digital system design, educational and industrial settings frequently rely on digital circuit schematics during initial planning stages or for producing small-scale prototypes. Hardware Description Language (HDL) such as VHDL and Verilog are commonly employed as the development progresses. However, there exists a challenge when it comes to generating HDL code from freehand sketches for simulation purposes, as this task is typically carried out manually. Existing design automation tools are incapable of handling sketch inputs effectively. To address this issue, this paper introduces an innovative system designed to automatically identify and convert hand-drawn logic circuits into VHDL code. This system can seamlessly integrate with existing Electronic Design Automation (EDA) systems, streamlining the design process. Our approach harnesses the power of machine learning, neural networks and image processing techniques to achieve exceptionally high accuracy and robustness in this conversion process. We also curated a substantial and comprehensive dataset of sketched logic circuits and trained our system on this dataset, resulting in an impressive accuracy rate exceeding 89%. The potential applications and advantages of our system extend to both educational and industrial settings. Furthermore, the system’s adaptability applies to various domains involving sketch-based design methodologies.