Transient current sharing in parallel GaN FETs: The role of parasitic capacitances

This paper examines the impact of parasitic capacitances on the dynamic current sharing behaviour of Gallium Nitride (GaN) field-effect transistors (FETs) operating in parallel configurations. As GaN technology continues to gain prominence in high-performance power electronic systems, paralleling multiple devices has become a common strategy to increase current-handling capability. However, non-idealities such as parasitic elements introduce significant challenges in achieving balanced current distribution during switching transients. To examine these effects, a custom-designed experimental platform was developed, enabling independent gate control and current measurement for each GaN FET via dedicated source shunt resistors. The test setup facilitates the precise characterisation of transient behavior and allows for detailed analysis under controlled conditions. Complementary simulation studies were conducted to support the experimental results and to identify key parameters influencing transient current mismatch. The paper highlights the critical role of parasitic capacitances—both device-internal and layout-induced—in shaping the peak transient current distribution among parallel devices during turn-on events. A methodology is proposed to estimate the maximum allowable parasitic capacitance that ensures the peak pulse current remains within the safe operating limits specified by device manufacturers. This insight is essential for the robust design of multi-device GaN switching assemblies, where overcurrent during transients can compromise long-term reliability or lead to failure. The outcomes of this research provide practical design guidelines for optimising parallel GaN switch configurations, with particular attention to parasitic management, driver strategy, and layout considerations. These contributions support the development of reliable and high-efficiency GaN-based power modules for advanced power conversion applications.