PEDC: A High-Efficacy, Parallel, and Configurable Distributed Control Architecture Design Approach of Cryptographic CGRA Utilizing the Control Subgraph Partitioning and Expansion Method

Coarse-grained reconfigurable architectures (CGRAs) are increasingly employed as cryptographic accelerators due to their efficiency and flexibility. Existing studies on security-oriented CGRAs primarily focus on scaling or optimizing the data path, while comparatively little attention has been given to the control path. Recently, a general-purpose processing core or configuration system has been widely adopted as the controller of CGRA. While this approach significantly reduces the design and application complexity of CGRAs, it does so at the expense of control efficacy and flexibility. To address this issue, a configurable distributed control (D-C) architecture design approach (referred to as PEDC) is proposed, which enhances the parallel processing capability of CGRA by improving control flexibility. There are four key technologies in PEDC. First, control subgraphs are automatically partitioned to define the control scopes of controllers and extract the control nodes of the control framework. Second, control dependency relationships are extracted from the control flow graph to link the control nodes. Third, a control architecture graph is constructed by establishing master-slave relationships between process control nodes capable of independent task process control and other nodes. Lastly, design models for the input scheduling controller, output scheduling controller, cluster controller, and task process controller are presented. The PEDC approach essentially transforms the CGRA into a multi-instruction stream, multi-data stream processor. D-C architectures with various scales are implemented based on 40-nm CMOS technology. With the PEDC approach, multiple pipelines and independent tasks can be processed simultaneously, regardless of the array structure or algorithm type. Compared with the traditional control method, the PEDC achieves a 4.5 × execution efficiency. Compared with related reconfigurable architectures, PEDC enables CGRAs to be more functionally flexible and achieve a better full-load throughput.