Integrating an open-source soft-GPU overlay with RISC-V control and high-bandwidth memory
Image and signal processing workloads are widely deployed on Graphics Processing Units (GPUs) for high throughput and on Field-Programmable Gate Arrays (FPGAs) for hardware specialization and energy efficiency. Soft GPU overlays on FPGAs aim to combine these advantages, yet existing solutions often depend on fixed hard processors or impose platform constraints that limit portability. This work extends a popular open-source soft GPGPU overlay to integrate a soft RISC-V control plane and enable compatibility with High-Bandwidth Memory (HBM2). The resulting system can be instantiated on FPGA boards without a hard ARM processor, improving portability, simplifying system integration, and broadening deployability. Across representative image and signal processing kernels, the soft GPGPU achieves geometric-mean speedups of 114.60 × over a scalar soft RISC-V core and 19.72 × over a hard ARM core, demonstrating substantial performance benefits while retaining FPGA reconfigurability. HBM2 integration further benefits bandwidth-sensitive workloads by increasing sustained throughput and reducing the performance bottlenecks associated with off-chip memory access. Collectively, these results indicate that GPU-like programmability and performance can be delivered on reconfigurable platforms without reliance on hard CPU subsystems, providing a portable and scalable foundation for embedded vision and DSP acceleration.
Authors
- Marc Reichenbach (ORCID: https://orcid.org/0000-0002-9687-6247)
- Keyvan Shahin (ORCID: https://orcid.org/0000-0002-6694-2821)
- Christian Herglotz (ORCID: https://orcid.org/0000-0001-8975-0171)
- Diana Göhringer (ORCID: https://orcid.org/0000-0003-2571-8441)
- Alireza Syavashi
- Hector Gerardo Muñoz Hernandez
- Michael Hübner
- Mahdi Taheri
- Muhammad Ali
Institutions
- Tallinn University of Technology (EE)
- Hanseatic University Rostock (DE)
- Hochschule für Technik und Wirtschaft Dresden – University of Applied Sciences (DE)
- University of Rostock (DE)
- Brandenburg University of Technology Cottbus-Senftenberg (DE)
- Technische Universität Dresden (DE)
Publication Details
- Journal
- Journal of Systems Architecture
- Published
- 2026-02-23
- DOI
- https://doi.org/10.1016/j.sysarc.2026.103736
- Primary Topic
- Parallel Computing and Optimization Techniques
- Type
- article
- Field-Weighted Citation Impact
- 0.00