Charge Loss Modeling and Lifetime Prediction in 28 nm HKMG SONOS Memory Using a Temperature-Dependent T-Model

The continuous scaling of microelectronic technology nodes has imposed fundamental physical constraints on conventional floating-gate (FG) non-volatile memory, driving the adoption of charge-trapping memory such as Silicon–Oxide–Nitride–Oxide–Silicon (SONOS) technology. SONOS devices offer advantages in scalability, endurance, and compatibility with advanced CMOS processes, yet their high-temperature reliability remains challenging due to charge loss mechanisms influenced by device structure and material properties. In this work, we systematically evaluate the reliability of two-transistor SONOS memory fabricated using a 28 nm high-K metal gate (HKMG) process. A refined temperature-dependent charge loss model (T-model) is introduced, which, by incorporating a characteristic temperature parameter (T0) that captures the dynamic shift in activation energy, fundamentally departs from the constant-activation energy assumption of the conventional Arrhenius model. This approach more accurately describes charge retention behavior across a wide temperature range. Experimental results demonstrate excellent device performance, including endurance exceeding 104 program/erase cycles at 85 °C and data retention over 10 years at 85 °C. The T-model shows strong agreement with measured data, providing a physically grounded framework for predicting long-term reliability. This study not only validated a novel charge loss model, providing insights for predicting the failure time of SONOS memory, but also demonstrated that HKMG-integrated SONOS memory exhibits high reliability.