A Low-Power Double-Edge-Triggered Flip-Flop Architecture Employing Cascoded Pull-Up and Pull-Down Transistors

In digital circuits, Double Edge Triggered Flip-Flops (DETFFs) have emerged as a crucial component, specifically in applications that necessitate precision timing. Their flexible design, which allows them to be constructed using a variety of gate logic forms such as Complementary Metal-Oxide-Semiconductor (CMOS) or Transistor–Transistor Logic (TTL), and in multiple configurations including D, JK, and T flip-flops, accentuates their ubiquity in digital circuitry. The present study seeks to augment the current under-standing of static double-edge triggered pulsed flip-flops (DETFFs) and introduces a novel structure. This proposed design incorporates cascaded pull-up and pull-down Metal-Oxide-Semiconductor (MOS) transistors for both the clock and D inputs. We simulated this new configuration at three different frequencies—50 kHz, 100 kHz, and 1 MHz—using Tanner SPICE (TSPICE), operating at a voltage of 1.3 V. Our findings reveal a significantly reduced power consumption by the proposed circuit compared to existing designs. With an improvement exceeding 95% in the Power-Delay Product (PDP), this proposed DETFF emerges as a promising contender for implementation in low voltage, low power digital circuits. The substantial PDP improvement and the power efficiency of our proposed DETFF design underscore its potential in revolutionizing low-power digital circuit design. Thus, this work concentrates on modelling an Energy-Efficient Unequal Cluster Management using the Elephant Herd Optimization approach (EEUCM-EHO) that considers the distance explicitly to reduce energy consumption. The maximal nodes transmission ability is provided with higher significance using the clustering strategy of EHO. Moreover, EEUCM-EHO concentrates on clustering strategies. The anticipated EEUCM-EHO is evaluated with various performance metrics like average energy consumption, network lifetime, average residual energy, and the number of alive nodes.

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Publication Details

Journal
Journal of Nanoelectronics and Optoelectronics
Published
2025-10-01
DOI
https://doi.org/10.1166/jno.2025.3828
Primary Topic
Low-power high-performance VLSI design
Type
article
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article

A Low-Power Double-Edge-Triggered Flip-Flop Architecture Employing Cascoded Pull-Up and Pull-Down Transistors

R. Prabakaran, M. Saravanan, T. Ashok, A. Sridevi
Journal of Nanoelectronics and Optoelectronics
Low-power high-performance VLSI design
article

A Low-Power Double-Edge-Triggered Flip-Flop Architecture Employing Cascoded Pull-Up and Pull-Down Transistors

R. Prabakaran, M. Saravanan, T. Ashok, A. Sridevi
article en

Abstract

In digital circuits, Double Edge Triggered Flip-Flops (DETFFs) have emerged as a crucial component, specifically in applications that necessitate precision timing. Their flexible design, which allows them to be constructed using a variety of gate logic forms such as Complementary Metal-Oxide-Semiconductor (CMOS) or Transistor–Transistor Logic (TTL), and in multiple configurations including D, JK, and T flip-flops, accentuates their ubiquity in digital circuitry. The present study seeks to augment the current under-standing of static double-edge triggered pulsed flip-flops (DETFFs) and introduces a novel structure. This proposed design incorporates cascaded pull-up and pull-down Metal-Oxide-Semiconductor (MOS) transistors for both the clock and D inputs. We simulated this new configuration at three different frequencies—50 kHz, 100 kHz, and 1 MHz—using Tanner SPICE (TSPICE), operating at a voltage of 1.3 V. Our findings reveal a significantly reduced power consumption by the proposed circuit compared to existing designs. With an improvement exceeding 95% in the Power-Delay Product (PDP), this proposed DETFF emerges as a promising contender for implementation in low voltage, low power digital circuits. The substantial PDP improvement and the power efficiency of our proposed DETFF design underscore its potential in revolutionizing low-power digital circuit design. Thus, this work concentrates on modelling an Energy-Efficient Unequal Cluster Management using the Elephant Herd Optimization approach (EEUCM-EHO) that considers the distance explicitly to reduce energy consumption. The maximal nodes transmission ability is provided with higher significance using the clustering strategy of EHO. Moreover, EEUCM-EHO concentrates on clustering strategies. The anticipated EEUCM-EHO is evaluated with various performance metrics like average energy consumption, network lifetime, average residual energy, and the number of alive nodes.

Journal of Nanoelectronics and OptoelectronicsVol. 20(10)
Karunya University (IN), National Institute of Technology Tiruchirappalli (IN), SRM Institute of Science and Technology (IN), Anna University, Chennai (IN)
Affordable and clean energy
Openalex Percentile: Top 35%
Low-power high-performance VLSI design
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