A Genetic Algorithm-Based Optimization Method for Ordered Escape Routing in BGA PCBs Under Non-Crossing and Single-Capacity Constraints

The increasing functional complexity and high-density integration of integrated circuits (ICs) present formidable routing challenges for printed circuit boards. Specifically for components utilizing high-density Ball Grid Array and other Grid Pin Array (GPA) packages, achieving efficient and reliable ordered escape routing is critical. This routing must strictly satisfy non-crossing and channel capacity constraints, which often become the bottleneck determining design success. Traditional manual or heuristic methods are increasingly inadequate for meeting the complexity and optimization demands of modern high-density designs. To address this challenge, this study proposes an innovative, automated routing strategy that leverages the robust search and optimization capabilities of the genetic algorithm (GA). We formulate the ordered escape routing problem on BGA/GPA as a rigorous combinatorial optimization problem. Through the GA mechanism, the core research objective is to explore the vast solution space and achieve the minimization of the total routing cost. This research establishes an automated routing framework capable of providing cost-effective escape routing solutions for high-density BGA, while strictly satisfying the non-crossing and single-capacity constraints. The proposed methodology not only significantly enhances routing efficiency and success rates but also provides essential technical support for the design and manufacturing processes of complex electronic products. For instance, in the simulation case of Case 7 (a 25 × 26 array with 60 active pins), this method achieved a routing compression ratio of 0.8230, equivalent to a 17.70% reduction in the total routing length, fully demonstrating the superior performance of the proposed algorithm in optimizing the routing cost.

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Publication Details

Journal
Applied Sciences
Published
2026-02-18
DOI
https://doi.org/10.3390/app16042010
Primary Topic
VLSI and FPGA Design Techniques
Type
article
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article

A Genetic Algorithm-Based Optimization Method for Ordered Escape Routing in BGA PCBs Under Non-Crossing and Single-Capacity Constraints

Chia‐Hsuin Chang, Dun-Wei Cheng
Applied Sciences
VLSI and FPGA Design Techniques
article

A Genetic Algorithm-Based Optimization Method for Ordered Escape Routing in BGA PCBs Under Non-Crossing and Single-Capacity Constraints

Chia‐Hsuin Chang, Dun-Wei Cheng
article en

Abstract

The increasing functional complexity and high-density integration of integrated circuits (ICs) present formidable routing challenges for printed circuit boards. Specifically for components utilizing high-density Ball Grid Array and other Grid Pin Array (GPA) packages, achieving efficient and reliable ordered escape routing is critical. This routing must strictly satisfy non-crossing and channel capacity constraints, which often become the bottleneck determining design success. Traditional manual or heuristic methods are increasingly inadequate for meeting the complexity and optimization demands of modern high-density designs. To address this challenge, this study proposes an innovative, automated routing strategy that leverages the robust search and optimization capabilities of the genetic algorithm (GA). We formulate the ordered escape routing problem on BGA/GPA as a rigorous combinatorial optimization problem. Through the GA mechanism, the core research objective is to explore the vast solution space and achieve the minimization of the total routing cost. This research establishes an automated routing framework capable of providing cost-effective escape routing solutions for high-density BGA, while strictly satisfying the non-crossing and single-capacity constraints. The proposed methodology not only significantly enhances routing efficiency and success rates but also provides essential technical support for the design and manufacturing processes of complex electronic products. For instance, in the simulation case of Case 7 (a 25 × 26 array with 60 active pins), this method achieved a routing compression ratio of 0.8230, equivalent to a 17.70% reduction in the total routing length, fully demonstrating the superior performance of the proposed algorithm in optimizing the routing cost.

Applied SciencesVol. 16(4)
National Yunlin University of Science and Technology (TW)
Openalex Percentile: Top 51%
VLSI and FPGA Design Techniques
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