Performance investigation of non-volatile memories for energy-efficient on-chip L2 caches

Abstract This paper explores the potential of emerging non-volatile memory (NVM) technologies – including Spin-Transfer Torque Magnetic RAM (STT-MRAM), Spin-Orbit Torque MRAM (SOT-MRAM), Voltage-Controlled Magnetic Anisotropy (VCMA)-based MRAM, and Resistive RAM (RRAM) – to reshape the CPU memory hierarchy landscape. These NVMs offer several advantages over conventional SRAM, such as ultra-low leakage, high density, non-volatility, and scalability. We present a comprehensive comparison between these technologies and SRAM across cache capacities ranging from 16KB to 8MB and associativity values from 1 to 16 at 22 nm node. The results reveal that SRAM outperforms NVMs at smaller cache sizes, while NVMs – particularly SOT-MRAM and aggressive STT-MRAM – become favourable beyond 128KB. For a 512KB L2 cache, SOT-MRAM and STT-A MRAM achieve energy-area-delay product (EADP) improvements of 73.7% and 67.8% over SRAM, which further improve to 97.2% and 98.4% at 2MB. However, RRAM and STT-MRAM show significantly higher write energy costs – up to 18.3× and 21.8× that of SRAM at 512KB. In terms of leakage, STT-A MRAM achieves the best results, reducing leakage by nearly 99%, followed by STT and SOT-MRAM. Interestingly, the impact of associativity variation becomes less pronounced at larger cache sizes.