Design of a distributed thermal sensor network embedded in photonic devices for reliable optical network-on-chip

Abstract Optical network-on-chip (ONoC) architectures offer high bandwidth and sub-nanosecond latencies for today’s multicore chips, yet they fall short of realistic performance due to thermally driven drift in silicon photonic devices. Research shows that 1 K of drifting temperature leads to 20–30 pm realignment in microring resonators (MRR) resonance drift wavelengths, increasing bit error rate (BER), latency, and random routing decisions. This study details the fully designed, tested distributed thermal sensor network (DTSN), which lies beneath the microrings (MRRs) to enable localized spatial thermal awareness correction. Achievements range from device-level design to ANSYS-based multiphysical modeling, drift predictor accuracy, and system-level confirmation through photonic NoC simulators. Ultimately, this study finds that the DTSN reduces BER by 40–70 %, latency by 20–30 %, and removes localized hotspots from pH devices, thereby increasing wavelength stability across the chip with approximately 40 % less power consumption in the heaters.