Design and Reliability Analysis of a Pipeline RISC-V Processor Core

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SPIRE - Sciences Po Institutional REpository
Published
2026-03-17
Primary Topic
Embedded Systems and FPGA Applications
Type
article
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article

Design and Reliability Analysis of a Pipeline RISC-V Processor Core

Wesley Grignani, Luigi Dilillo, Santos, Douglas, A, Carolina Imianosky et al.
SPIRE - Sciences Po Institutional REpository
Embedded Systems and FPGA Applications
article

Design and Reliability Analysis of a Pipeline RISC-V Processor Core

Wesley Grignani, Luigi Dilillo, Santos, Douglas, A, Carolina Imianosky, Melo, Douglas, R
article en

Abstract

No abstract available for this paper.
SPIRE - Sciences Po Institutional REpository
Institut d'Électronique et des Systèmes (FR), Universidade do Vale do Itajaí (BR)
Fundação de Amparo à Pesquisa e Inovação do Estado de Santa Catarina, Université de Montpellier, Région Occitanie Pyrénées-Méditerranée, HORIZON EUROPE Framework Programme
Industry, innovation and infrastructure
Openalex Percentile: Top 56%
Embedded Systems and FPGA Applications
Open Access PDFOpenAlex
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