A Novel 22 kW Bidirectional All-GaN Integrated Onboard Charger Using a 3L-NPC and Interleaved Dual-Buck With Low Common Mode Voltage

This paper presents a simulation study on a 22 kW bidirectional all-GaN integrated onboard charger (iOBC) that combines a three-level neutral-point-clamped (3L-NPC) AC-DC front end with a two-phase interleaved dual-buck DC-DC back end. Referencing both stages to a split DC link limits device stress to half the bus voltage, enabling the use of 650 V GaN devices and supporting high switching frequency with improved power density and efficiency. The topology inherently lowers common-mode voltage; simulation results show near-complete cancellation at the DC/DC output. The control implemented is a grid-synchronised cascaded dq scheme for the 3L-NPC and phase-shifted interleaving with per-leg current control for the DC-DC stage. PLECS results in G2V and V2G operation confirm near-unity power factor with THD at 2.5 % at 22 kW, drain-source voltage peaks around half of the DC link voltage. By keeping each switch within half-bus voltage while shifting ripple to twice the switching frequency, the proposed architecture enables a compact, efficient, and scalable charger platform.

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Published
2025-12-01
DOI
https://doi.org/10.1109/spec64875.2025.11376879
Primary Topic
Silicon Carbide Semiconductor Technologies
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article
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article

A Novel 22 kW Bidirectional All-GaN Integrated Onboard Charger Using a 3L-NPC and Interleaved Dual-Buck With Low Common Mode Voltage

Christian Klumpner, Ebraam Fakhuri, Rishad Ahmed, Ying Li
Silicon Carbide Semiconductor Technologies
article

A Novel 22 kW Bidirectional All-GaN Integrated Onboard Charger Using a 3L-NPC and Interleaved Dual-Buck With Low Common Mode Voltage

Christian Klumpner, Ebraam Fakhuri, Rishad Ahmed, Ying Li
article en

Abstract

This paper presents a simulation study on a 22 kW bidirectional all-GaN integrated onboard charger (iOBC) that combines a three-level neutral-point-clamped (3L-NPC) AC-DC front end with a two-phase interleaved dual-buck DC-DC back end. Referencing both stages to a split DC link limits device stress to half the bus voltage, enabling the use of 650 V GaN devices and supporting high switching frequency with improved power density and efficiency. The topology inherently lowers common-mode voltage; simulation results show near-complete cancellation at the DC/DC output. The control implemented is a grid-synchronised cascaded dq scheme for the 3L-NPC and phase-shifted interleaving with per-leg current control for the DC-DC stage. PLECS results in G2V and V2G operation confirm near-unity power factor with THD at 2.5 % at 22 kW, drain-source voltage peaks around half of the DC link voltage. By keeping each switch within half-bus voltage while shifting ripple to twice the switching frequency, the proposed architecture enables a compact, efficient, and scalable charger platform.

University of Nottingham (GB)
Affordable and clean energy
Openalex Percentile: Top 36%
Silicon Carbide Semiconductor Technologies
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