TCAD Simulation of STI Depth and SiO2/Silicon Interface Trap Modulation Effects on Low-Frequency Noise in HZO-Based Nanosheet FETs

This study analyzed the low-frequency noise characteristics of nanosheet field-effect transistors (NSFETs) using technology computer-aided design (TCAD) simulations. In particular, the effects of shallow trench isolation (STI) depth and gate-insulator interface trap density on the device's flicker noise power spectral density (PSD) were systematically evaluated. The simulation results show that as STI depth increases, excessive trap charges formed in the STI oxide can deplete or invert the substrate beneath the STI layer, reducing the threshold voltage of parasitic transistors and thereby increasing flicker noise. In contrast, the shallow STI structure's trapped charge density was found to be lower than in thicker structures. Additionally, when an HfO₂-ZrO₂ (HZO)-based ferroelectric insulator is applied, improved gate-field control and reduced trap-induced noise are observed compared to HfO₂. Optimization results indicate that the optimal noise performance is achieved with an STI depth of 3 nm and a SiO₂/silicon interface trap density of 1 × 10¹⁰ eV^-1cm^-2. This study provides a design direction for low-noise NSFETs through structural (STI) and material (interface traps and HZO) optimization and is expected to contribute to the development of next-generation low-power, high-reliability logic devices.