FPGA Programmable Logic Block Architecture with High-Density MAC for Deep Learning Inference

Compared to half- or single-precision floating-point, reducing the precision of Deep Neural Network (DNN) inference accelerators can yield significant efficiency gains with little to no accuracy degradation by enabling more multiplication operations per unit area. The variable precision capabilities of FPGAs are extremely valuable, as a wide range of precisions fall on the Pareto-optimal curve of hardware efficiency versus accuracy, with no single precision dominating. We propose seven variants across three types of logical block designs to improve the area efficiency of multiply accumulate (MAC) implemented in soft structures. Ultimately, we use COFFE and VTR tools to fully evaluate these enhancements. The 2-bit adder BLE (ADD2_BLE) architecture achieves a 7.3% area optimization with only a 1.7% increase in tile area by improving the fracturability of LUTs in the baseline BLE and adding an additional 1-bit adder. However, this comes at the expense of reduced speed. The 9-bit Compact Multiplier (CMUL) architecture based on ADD2_BLE achieved the greatest optimization among the six variants using the Compact Multiplier (CMUL). On average, it reduces the DAP result by up to 72%. Nonetheless, it results in a 13% increase in logic tile area for universal benchmarks that do not use multiplication.