A New Strategy to Design Reconfigurable Rivest–Shamir–Adleman (RSA) Accelerators

ABSTRACT Ensuring security and processing speed are crucial attributes in today's computing applications. One of the most commonly used encryption systems is the Rivest–Shamir–Adleman (RSA), whose strength lies in the difficulty of breaking its keys. However, to continue guaranteeing adequate levels of protection, the size of these keys tends to grow over time, resulting in more complex encryption/decryption processes and longer operating times. This paper describes an RSA cryptographic accelerator soft‐core as an alternative to state‐of‐the‐art implementations solely based on efficient Montgomery modular executions. The proposed solution utilizes compression‐based modular multipliers to handle the complexity of the modular‐exponentiation operations. Furthermore, we further enhance performance by introducing a pseudomodulo strategy for processing the information in more efficient hardware (i.e., ) and then correcting the results back to the original modulo . The system was implemented using the MAX 10 10M50DAF484C7G FPGA and was integrated into a NEORV32 RISC‐V core. Results show that the new compression‐based multipliers, particularly with the use of pseudomoduli, provide significantly higher gains in terms of delay, delay logic elements, and execution time than approaches based on direct modulo multiplication and with the state of the art based on Montgomery multiplication.