Simulation of a Floating Gate Transistor Based on a Graphene/h-BN/MoS2 van der Waals Heterojunction

Silicon (Si) technology-based transistors are characterized by significant standby power dissipation. However, Si transistors cannot be scaled at gate lengths less than 5 nm due to short-channel effects. The required high synaptic densities disallow the use of Si devices for neuromorphic applications. There are numerous electrically erasable nonvolatile memory devices with different electronic architectures, among which floating gate transistors represent the most promising class. In this study, a floating gate transistor based on a graphene/h-BN/MoS2 van der Waals heterojunction is considered, and a multiscale model of the device is constructed and implemented. Using density functional theory (DFT) methods, the physical properties of the heterostructure are studied. A simplified Shichman–Hodges model is used to study the transfer characteristics. It is demonstrated that the floating gate is charged by the Fowler–Nordheim tunneling effect and direct tunneling. The calculations show that the presented device demonstrates high performance (at a 9 V gate voltage, the write time is 50 ns). The memory window can be adjusted by changing the voltage sweep range of the control electrode. In addition, the device demonstrates the characteristics of a biological synapse, such as impulse potentiation and plasticity, which are expressed in the ability to tune the channel conductivity by an electric impulse fed to transistor gate. These features are important for the learning process, and thus open up the possibility of using the transistor for neuromorphic applications.