Analysis of Instability of Dynamic On-Resistance in p-GaN eHEMTs by Vds Bias and Temperature

In this paper, we investigate the instability of the dynamic on-state resistance (RON) under hard-switching conditions for four different p-GaN enhancement-mode high-electron-mobility transistors (eHEMTs). These investigations are facilitated by a clamping circuit parallel to the device under test (DUT) and a double pulse test (DPT), conducted under varying off-state Drain-to-Source voltage (Vds) stress and temperature. The influence of Vds bias stress and temperature are examined, and a brief analysis of the underlying mechanisms is provided. It was observed that the dynamic RON of each device exhibits a non-monotonic dependence on the Vds bias, decreasing as the voltage increases with rising temperature due to impact ionization and the generation of positive charges in the buffer layer. Although higher temperatures generally lead to increased dynamic RON, mechanisms exist that generate positive charges to compensate for the effects of negative charge trapping at elevated temperatures. Furthermore, different devices demonstrate varied sensitivities to Vds bias and temperature.

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Publication Details

Journal
Bristol Research (University of Bristol)
Published
2025-06-30
DOI
https://doi.org/10.30420/566541210
Primary Topic
GaN-based semiconductor devices and materials
Type
article
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article

Analysis of Instability of Dynamic On-Resistance in p-GaN eHEMTs by Vds Bias and Temperature

Saeed Jahdi, Bernard H. Stark, Xiangyu Wang, Jun Wang
Bristol Research (University of Bristol)
GaN-based semiconductor devices and materials
article

Analysis of Instability of Dynamic On-Resistance in p-GaN eHEMTs by Vds Bias and Temperature

Saeed Jahdi, Bernard H. Stark, Xiangyu Wang, Jun Wang
article en

Abstract

In this paper, we investigate the instability of the dynamic on-state resistance (RON) under hard-switching conditions for four different p-GaN enhancement-mode high-electron-mobility transistors (eHEMTs). These investigations are facilitated by a clamping circuit parallel to the device under test (DUT) and a double pulse test (DPT), conducted under varying off-state Drain-to-Source voltage (Vds) stress and temperature. The influence of Vds bias stress and temperature are examined, and a brief analysis of the underlying mechanisms is provided. It was observed that the dynamic RON of each device exhibits a non-monotonic dependence on the Vds bias, decreasing as the voltage increases with rising temperature due to impact ionization and the generation of positive charges in the buffer layer. Although higher temperatures generally lead to increased dynamic RON, mechanisms exist that generate positive charges to compensate for the effects of negative charge trapping at elevated temperatures. Furthermore, different devices demonstrate varied sensitivities to Vds bias and temperature.

Bristol Research (University of Bristol)
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GaN-based semiconductor devices and materials
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