Graph Neural Network-Based Glitch Rate Prediction at the Signoff Stage

Dynamic power consumption has become a dominant concern in modern digital designs, with reports indicating that glitches can contribute up to 40% of total dynamic power consumption. Traditional approaches to evaluating glitch power, such as static analysis and dynamic simulation, face tradeoffs between accuracy and efficiency. This article presents a Graph Neural Network (GNN)-based model that leverages machine learning to estimate glitch rates. The model learns the structural and timing features of the circuit and utilizes a small set of input patterns to predict glitch rates after gate sizing-based Engineering Change Order (ECO). By integrating the predicted glitch rates with a commercial power analysis tool, the proposed method enables rapid identification of glitch hotspots, accelerating power optimization during the signoff stage. Experimental results highlight the effectiveness of the proposed model, achieving an average Root Mean Square Error (RMSE) of 0.0867 and a correlation coefficient of 0.9100 in glitch rate prediction. Moreover, the approach identifies glitch hotspots with high accuracy, correctly labeling 83.4% of the top 5% highest glitch power gates and 89.78% of the top 10%. Compared to relying solely on commercial tools for glitch power estimation within the optimization flow, the proposed method reduces runtime by an average of 35.78% when the iteration count matches the circuit’s logic level.