Energy-Aware Design and Performance Analysis of Through-Oxide Thermal Vias (TOTVs) via Finite Element Analysis and Driven Optimization

This study employs three-dimensional finite element analysis (FEA) to investigate the coupled thermo-mechanical behavior and electrical energy characteristics of Through-Oxide Thermal Via (TOTV) structures under thermal cycling conditions, with an emphasis on quantifying trade-offs between mechanical reliability and electrical efficiency. A unified three-dimensional thermo-mechanical and electrical modeling framework is established to capture stress concentration, deformation behavior, and geometry-dependent parasitic effects in a physically consistent manner, with observed trends showing qualitative agreement with prior TOTV-related studies. Single-objective optimization results indicate that geometric refinement can reduce the maximum principal stress from 119.54 MPa to 97.64 MPa, corresponding to an 18.3% relative improvement within the adopted modeling assumptions. However, such mechanically optimized configurations are accompanied by increased parasitic capacitance, leading to higher dynamic energy consumption. This observation quantitatively highlights the inherent conflict between structural integrity and electrical energy efficiency in dense TOTV arrays. To systematically explore this trade-off, a Multi-Objective Genetic Algorithm (MOGA) is employed to construct a Pareto-optimal design set. A representative compromise solution—characterized by a via radius of 21.246 µm, pitch of 69.172 µm, and copper thickness of 1.011 µm—achieves a 14.8% reduction in maximum principal stress and a 72% reduction in axial deformation (0.0156 µm), while avoiding the severe energy penalties observed in reliability-only optimizations. Rather than emphasizing absolute performance prediction, the proposed framework serves as an energy-aware design-space exploration methodology, providing quantitative insight into the relative severity of mechanical–electrical trade-offs for future high-density 3D integrated circuits and silicon photonics applications.