Reliability Architectures for High-Performance Processors: A Survey and Outlook

Reliability assurance has traditionally been associated with safety-critical domains such as aerospace, autonomous driving, and other cyber-physical systems. Today, the risk profile extends to mainstream computing: relentless scaling for performance and energy efficiency has increased design complexity and core counts, pushed frequencies higher, and lowered operating voltages at ever-smaller process nodes (3 nm and below). This shift motivates a revisit of reliability for high-performance processors. This paper surveys three families of reliability architectures: hardware-centric lockstep, software-centric techniques (software redundancy and periodic self-test), and heterogeneous cooperative verification (HCV). We place these approaches within a common taxonomy that spans evaluation aspects such as redundancy placement, coupling strength, verification granularity, detection latency, recovery strategy, and cost. Based on the survey, we argue that HCV is the most promising direction for high-performance processors, and we outline the key challenges to realizing a full-fledged HCV design. We hope this survey serves as a practical map for reliability assurance in future high-performance processors.