Recent insights in direct extraction of access resistance components in NSFET and CFET devices with the cascaded transistor method

Abstract In this work, we present recent insights into access resistance extraction based on a cascaded transistor test-structure. In the first part, we propose a new methodology to isolate the channel resistance component by varying the overdrive voltage. This procedure is applied to both n- and p-NSFET devices to analyze the impact of rapid thermal anneal treatment and inner spacer size variation, respectively. Results are assessed with both electrical measurements and TCAD simulations. In the second part, we present an upgraded cascaded transistor test-structure for CFET devices offering additional functionalities. Initial results are presented, analyzing the impact of the wiring scheme and the contact size. Finally, contact resistivity extraction is performed and compared to large transmission line test-structures for NSFET and CFET devices, respectively.