Synergistic Effects of Additive Engineering in Enhancing the Performance of Sn–Pb Perovskite Thin‐Film Transistors and Derived Logic Circuits

Solution-processed metal halide perovskite transistors possess intrinsic characteristics that hold promise for integration with n-type semiconductors such as fullerene (C₆₀) in CMOS-like circuits. Yet, their performance and stability remain inferior to n-type counterparts due to inefficient in-plane charge transport and defect-induced instabilities. This study proposes a rational additive engineering strategy using 4,8-dihydrobenzo[1,2-b:4,5-b']dithiophen-4,8-dione (BDTD) to regulate nucleation and crystallization of MA_0.4FA_0.6Sn_0.5Pb_0.5I₃ films. BDTD alleviates microstrain, suppresses Sn⁴⁺-related defects, and passivates undercoordinated Sn and Pb ions, forming smoother films with enlarged grains. Compared to control devices, the optimized transistor achieves an increase by an order of magnitude in hole mobility (4.1 vs. 0.38 cm² V^-1 s^-1) and a substantially improved on/off ratio (1.8 × 10⁵ vs. 3.1 × 10⁴). Moreover, the BDTD-treated transistors exhibit excellent reproducibility and operational stability under inert conditions without encapsulation. Furthermore, surface passivation using tetrabutylammonium hexafluorophosphate (TBAPF6) reduces interfacial traps, improving reliability and lowering the threshold voltage from 9.89 to 3.6 V. Finally, integration with an n-type C60 transistor yields a functional perovskite-C60 inverter, demonstrating strong potential for complementary logic applications. This work highlights the synergistic role of additive and interfacial engineering in overcoming intrinsic limitations of Sn-Pb perovskites, offering a viable pathway toward practical perovskite-based complementary electronics.