Influence of Parallelism in Vector-Multiplication Units on Correlation Power Analysis

The use of Neural Networks (NNs) in edge devices is increasing, introducing new security challenges related to the confidentiality of NNs. As edge devices often offer physical access, attacks targeting the hardware, such as Side-Channel Analysis (SCA), must be considered. To enhance the performance of NN inference, hardware accelerators are commonly employed. This work investigates the influence of parallel processing within such accelerators on correlation-based side-channel attacks that exploit power consumption. The focus is on neurons that are part of the same fully-connected layer, which run parallel and simultaneously process the same input value. The theoretical impact of concurrent Multiply-and-Accumulate (MAC) operations on overall power consumption is evaluated, as well as the success rate of Correlation Power Analysis (CPA). Based on the observed behavior, equations are derived that describe how the correlation decreases with increasing levels of parallelism. The applicability of these equations is validated using a vector-multiplication unit implemented on a Field Programmable Gate Array (FPGA). The theoretical boundary for successful CPA is found to be 15 parallel Processing Elements (PEs), while practical results show this limit is reduced to 8 PEs due to noise and Signal-to-Noise Ratio (SNR) reduction.