Scalable SoC Architecture for Parallel‐Pixel Classification of Hyperspectral Images Using Weighted‐Summation Kernel SVM

ABSTRACT Hyperspectral image (HSI) classification demands high‐performance processing and accuracy due to data dimensionality and computational complexity. The support vector machine (SVM) algorithm, which is renowned for its ability to manage high‐dimensional data through kernel techniques for classification tasks effectively, has shown promising results in HSI analysis and applications. Composite kernels enhance SVM efficacy by integrating multiple kernels to capture diverse data characteristics. Existing SVM algorithms based on composite kernels are susceptible to high latency, computationally intensive operations, and poor scalability, which makes it challenging to deploy efficiently on resource‐limited high‐performance platforms like field‐programmable gate arrays (FPGAs). The paper proposes a novel composite weighted‐summation kernel (WSK) that combines polynomial and hardware friendly kernels (HFKs). The WSK kernel has been integrated with SVM, resulting in a classifier named WSK‐SVM. Furthermore, a scalable FPGA‐based system on chip (SoC) architecture is developed for HSI classification using WSK‐SVM. The architecture implements a fast kernel approximation method to compute a HFK which eliminates multiplications. The architecture leverages spatial and temporal parallelism, efficiently aggregating processing into clusters of parallel binary WSK‐SVM classifiers using the one‐vs‐one (OvO) methodology. The approach is scalable and achieves a level of spatial parallelism that facilitates the concurrent classification of multiple pixels. Two different SoC boards were used to implement the design. One board was based on the Xilinx Zynq‐7000 and featured four parallel classifiers, and the second board was based on the Zynq UltraScale+ MPSoC and featured eleven parallel classifiers. High classification accuracy (>∖,99%) was achieved on benchmark datasets (Indian Pines, Pavia Centre, and Pavia University) using 8‐bit fixed‐point processing, resulting in negligible loss of floating‐point accuracy. Resource utilization on the PYNQ‐Z2 reached 78.37% for LUTs and 77.14% for BRAM, whereas on the ZCU‐104, it was 49.76% for LUTs and 95.19% for BRAM. Real‐time latency was as low as 1.26 per pixel (ZCU‐104, Pavia Centre dataset) with a throughput of up to 6.35 MBPS. The proposed architecture provides scalable and high‐performance solutions for onboard HSI classification under real‐time constraints.