Design and implementation of a nano-scale digital adder for quantum-based signal processing applications

Digital Signal Processing (DSP) is a significant area of electronics and telecommunication engineering that employs a variety of methods to improve the accuracy and reliability of digital communications. The mathematical manipulation of digital signals from the real world, such as speech, audio, video, temperature, pressure, or position, is known as DSP. To display, analyze, or convert signals into other proper forms, their underlying data must be processed. By gathering and analyzing the digital data, DSP assumes control. After that, it feeds the digital data back for practical application. In order to analyze these digital signals and extract critical insights or enhance specific signal characteristics, DSP uses a variety of algorithms, approaches, and procedures, often with sensors, transducers, filters (analog and switched capacitors), circuit implementations, and functional materials that allow for real-time responsiveness and high-performance signal interpretation. Exponentially expanded computations and signal processing designs proportionally escalated the need to accelerate processing velocities. Contemporary systems in real-time image and signal manipulations require rapid arithmetic procedures that satisfy the requirements of high throughput. Multiplication, a kernel operation that holds a central position in many domains of those applications, hastened the development and advancement of high-speed multiplication circuits for several decades. One of the critical circuits that can improve the performance of all DSP systems is the multiplier, which plays a vital role in this system. However, modern DSP workloads from real-time filtering and spectral analysis to image pipelines are multiply intensive and constrained by tight energy, area, and latency budgets, especially in IoT/edge nodes. Conventional complementary metal-oxide–semiconductor (CMOS) multipliers face growing interconnect delays, leakage, and power limits. We address these challenges with a quantum-dot cellular automata (QCA)-based carry save adder that leverages a coplanar nanoarchitecture, which is core to shortening the critical path, decreasing the switching activity, and increasing the density. Compared with prior QCA carry save adders (CSA), our design reduces the number of used cells by 40.31%, area by 32.79%, and latency by 42.85%. These improvements translate directly to higher Multiply-Accumulate (MAC) unit throughput and deterministic response in DSP pipelines, enabling more capable real-time processing under strict edge-device power and form-factor constraints. The design is validated in QCADesigner and can be extended to support larger numbers of bits.