Heuristic & Expert-Guided Buffer Sizing for Neural Network Inference Applications on FPGAs

A crucial step in implementing neural network engines on FPGAs is the sizing of intermediate buffers between the pipeline stages. Undersizing buffers can lead to throughput degradation or deadlocks, oversizing wastes valuable device resources. Typically, buffer sizing is performed using simulation, employing solvers or implementing a search algorithm. With neu-ral networks rapidly growing in size, these approaches become time consuming and negatively impact design iteration times. In this work, we show that, in the domain of neural network inference on FPGAs, it is possible to avoid costly simulations or solvers for buffer sizing and use instead a method that relies on analytic modeling and heuristics. We incorporate our method into the FINN compiler and deliver up to three orders of magnitude faster buffer sizing. At the same time, the resulting buffer sizes are up to 9x smaller for a wide range of example neural networks such as MobileNet-V1 and ResNet-50 with negligible degradation in throughput.