Compression-Efficient Feature Extraction Method for a CMOS Image Sensor
To address the power constraints of the emerging Internet of Things (IoT) era, we propose a compression-efficient feature extraction method for a CMOS image sensor that can extract binary feature data. This sensor outputs six-channel binary feature data, comprising three channels of binarized luminance signals and three channels of horizontal edge signals, compressed via a run length encoding (RLE) method. This approach significantly reduces data transmission volume while maintaining image recognition accuracy. The simulation results obtained using a YOLOv7-based model designed for edge GPUs demonstrate that our approach achieves a large object recognition accuracy (APL50) of 60.7% on the COCO dataset while reducing the data size by 99.2% relative to conventional 8-bit RGB color images. Furthermore, the image classification results using MobileNetV3 tailored for mobile devices on the Visual Wake Words (VWW) dataset show that our approach reduces data size by 99.0% relative to conventional 8-bit RGB color images and achieves an image classification accuracy of 89.4%. These results are superior to the conventional trade-off between recognition accuracy and data size, thereby enabling the realization of low-power image recognition systems.
Authors
- K Kuroda
- Shunsuke Okura (ORCID: https://orcid.org/0000-0001-6422-3703)
- Hideki Shima
- Kota Yoshida (ORCID: https://orcid.org/0000-0003-1293-6415)
- Ryuichi Ujiie
- Yu Osuka
- Ryoya Iegaki
Institutions
- Ritsumeikan University (JP)
- Nisshinbo Holdings (Japan) (JP)
Publication Details
- Journal
- Sensors
- Published
- 2026-02-02
- DOI
- https://doi.org/10.3390/s26030962
- Primary Topic
- CCD and CMOS Imaging Sensors
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- Japan Society for the Promotion of Science