Recent advances in contact resistivity at metal–semiconductor interfaces for post-Moore nanoscale devices

Post-Moore nanoscale devices are driving the next wave of semiconductor advancement through three-dimensional architectures and material innovation. However, the shrinking source/drain contact area has made metal–semiconductor contact resistivity (ρc) a critical performance bottleneck. Conventional heavy doping techniques can no longer meet the stringent ρc requirement (<10−9 Ω cm2) for advanced technology nodes. Various strategies have been adopted to reduce it such as inserted silicide. However, ρc is typically limited to the range of 10−4–10−6 Ω cm2. Up until now, the mechanism behind these strategies is highly controversial. In this review, we comprehensively explain the underlying physical mechanisms governing ρc from the perspectives of Schottky barrier height and Fermi level pinning. Then, an analysis of state-of-the-art approaches for ρc reduction is reviewed, involving interface modification and oxide interlayer integration toward conventional semiconductor and advanced two-dimensional-based semiconductor. Finally, we discuss remaining challenges and proposing synergistic strategies on future research directions for achieving low contact resistivity in post-Moore nanoscale devices.