Bridging HDL Bits and Caffe: An Educational Path to AI Accelerator Design

An integrated educational pipeline is presented that bridges hardware description language (HDL) exercises with the Caffe deep learning framework, enabling progression from Verilog fundamentals to the deployment of convolutional neural network accelerators on field-programmable gate array (FPGAs). Parameterized, pipelined Verilog modules for convolution, pooling, ReLU activation, and fully connected layers are developed and verified using fixed test vectors. Meanwhile, a LeNet-5 model is defined and trained in Google Colab by using an AccDNN enabled Caffe build. Trained weights are exported, quantized to eight-bit fixed point by using Ristretto, and loaded into Verilog testbenches. A Python based co-simulation harness is provided to automate parameter extraction, regression testing, and bitaccurate comparison of outputs for hundreds of MNIST samples. The entire design is synthesized on an Artix-7 FPGA, achieving 25% LUT utilization, 50% DSP utilization, and 30% block RAM utilization at 100 MHz. An end-to-end inference latency of 0.156 ms is reported, corresponding to a 6,400 images per second throughput. Through the combination of HDL assignments, Caffe-based training, quantization analysis, and FPGA synthesis, learners are equipped with a complete workflow for accelerator design, verification, and performance evaluation. A controlled experiment involved 10 participants show that the proposed method is effective in supporting AI learning.