Design and implementation of high-level multilevel inverters: focusing on 15-level, 25-level, and 33-level topologies with asymmetrical configuration and optimal component choices

(English) The primary goal of this thesis is to establish multilevel inverter (MLI) topologies for industrial settings. Because of its numerous benefits, including low power dissipation on power supplies and low harmonic contents, MLI topologies are utilized in medium- and high-power applications, such as active power filters, FACTS devices, and machine currents. The chosen switching strategies are crucial in removing harmonic distortion from the output voltage provided by the MLI. Depending on the inverter's power requirements, different topologies and control strategies may be selected. However, they have several drawbacks over MLI, such as the need for separate power sources for each stage. Consequently, MATLAB/SIMULINK is used to simulate MLI. This work aims to offer a unique topology for a single-phase 15-level asymmetric MLI to minimize component requirements. The suggested design uses asymmetric DC sources to reach a maximum 15-level output voltage through an H-bridge topology. To enable a 25-level version appropriate for renewable energy applications, the original 15-level MLI structure is further improved, lowering system costs and dimensions. However, the higher component count in MLI presents reliability issues, particularly about the decrease of total harmonic distortion, which continues to be a research focus. Several factors are examined for the proposed 15-level- and the extended 25-level MLI, including total standing voltage, multilayer inverter cost function, and power loss. Next, it facilitates the integration of renewable energy sources and streamlines the use of components by contributing to a novel topology for 15-level asymmetric MLI. Even though multilevel inverters have many benefits, future developments in this field must address reliability issues related to overall harmonic distortion reduction. Then, a unique 33-level asymmetrical single-phase MLI is built, utilizing fewer components and a lower Total Standing Voltage (TSV) at the switches. Variable-rated switches are employed to lower the overall cost of the inverter, and the distribution of stress among the switches is carefully examined. The suggested design combines four asymmetrical DC sources with twelve switches to generate 33 voltage output levels. The inverter's performance is determined by many crucial factors, including TSV, efficiency, power loss, and cost function (CF). Using a range of combinational loads, the MLI was evaluated in dynamic load conditions with unforeseen load disturbances, and it was discovered to be stable throughout the operation. A thorough comparison uses graphical representations based on stress vi across switches, stress distribution, switch count, DC source count, gate driver circuits, component count factor, TSV, CF, and other existing topologies. It is demonstrated to be more efficient and better in every way. According to simulation and experiments, the Total Harmonic Distortion (THD) is within IEEE guidelines. The suggested framework was created in MATLAB/Simulink and tested using hardware in a lab environment.