Novel 3.3V RF-LDMOS in 16nm FinFET with the best RF and reliability trade-off enabling integrated Watt-level power amplifiers in connectivity SoC

A novel FinFET-based LDMOS device with a breakdown voltage of ~ 11 V and a record RF performance, with f<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MAX</inf> ~ 240 GHz and f<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> ~ 60 GHz, is presented. The device is composed of a thick gate oxide in the channel and two uniquely-connected dummy gates in the drain extension to optimize the electric field for reducing the device degradation due to hot carrier injection. The device reliability is further improved by using a baseline mask to partly block the P-well implant for smoothening the doping profile at the channel-drift junction. The device concept has been intensively assessed by TCAD, and fabricated in a 16nm FinFET node. A 5.5 GHz power-amplifier utilizing this novel LDMOS has been designed and taped-out on the same silicon. On-wafer measurements have been done to characterize DC, RF and reliability of these new devices. The measured characteristics, both on device and circuit level, confirmed the breakthrough RF performance and robustness of this new LDMOS compared to state-of-the-art LDMOS in FinFET processes.