First Systematic Characterization of Floating Body Effects in GAA Nanosheet 3D DRAM Access Transistors

As DRAM scaling advances toward dense 3D architectures with Si-based select transistors, floating body effects (FBE) emerge as a critical reliability concern due to transient leakage and associated data retention risks. This work presents the methodology for the first experimental extraction of floating-body-induced bipolar current (FBC) in nanosheet GAA 3D DRAM access transistors, leveraging transistor arrays to access low I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</inf> regimes inaccessible to single-device measurements. Two device populations, defined by high and low quasi-static (QS) leakage, are studied using a measurement protocol that isolates the transient parasitic BJT contribution. FBC amplitude is analyzed as a function of pre-charge time and leakage, revealing strong dependence on body charging dynamics. Extrapolation toward target I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</inf> specifications, supported by TCAD, shows that floating body effects are expected to be effectively suppressed. These findings provide key reliability guidance for Si-based 3D DRAM architectures.