A Multi-Self-Cascoded Voltage Reference with 2.73-ppm/V Line Sensitivity and 20.1-ppm/°C Temperature Coefficient at 0.45-V Supply

Recent advancements in low-power and low-voltage integrated circuits have spurred significant research interest, particularly for applications with demanding supply conditions. This work presents a single-branch voltage reference achieving exceptional immunity to supply voltage variations. Leveraging a ΔVGS-based approach, the design utilizes transistors with differentchannel lengths to exploit geometry-dependent threshold voltage differences, enabling effective temperature compensation.Additionally, a multi-self-cascoded technique enhances immunity to supply voltage variations. Post-layout simulations of a 0.18-μm CMOS design, operating with supply voltage as low as 0.45 V, demonstrate a line sensitivity of 2.73 ppm/V and a temperature coefficient of 20.1 ppm/◦C, with power consumption below 200 pW. The proposed architecture is shown to be a robust solution for implementing