Hardware architecture for LE Uncoded PHYs version5.3 Transmitter

This paper describes the design and implementation of a hardware architecture for a transmitter relative to Uncoded LE PHY version 5.3. This architecture is implemented in VHDL and verified by simulation using Vivado. The architecture is designed based on BLE standard v5.3 with specifications like frequency deviation, BT = 0.5, and BLE packet format (preamble, access address, payload, and CRC). The architecture is divided into two parts: frame generation and GFSK modulation. Obtained results validate the hardware implementability of a BLE 5.3 standard compliant transmitter. The architecture presented is a first prototype for future integration with RF front-ends and a comprehensive performance evaluation.