Panel Level Package: Reliability Evaluation of Double-sided Direct Copper Plated Interconnects on Embedded Power Die by Thermal and Electrical Stress Test

Recently, the use of panel-level packages has expanded for lower power consumption, thinner and smaller, as well as for cost reduction. Power supply systems for AI data centers are moving toward architectures that deliver power vertically, increasingly requiring reduced wiring resistance and inductance. Thinness is also an important factor due to the thickness limitations of the substrate core in which the power devices are embedded. In this situation, even the resistance and thickness of the bond line (BLT), such as solder and sintered Ag paste used for chip mounting, need to be removed. We presented a new packaging technology for chip embedding with direct copper plated interconnects on the double side of the power chip using 300 mm square panel-level process at IMAPS Advanced Packaging for Power Electronics 2024. The challenge with this direct copper plating process is that there is a large CTE mismatch between the chip and the copper plating. In addition, since there is no buffer layer such as die attach material, the bond interface is directly affected by high stresses, making bond reliability very important. Especially in power applications, they are used under higher stress conditions such as large currents and rapid temperature changes. Therefore, we need to evaluate the reliability of the interconnect not only for environmental testing, but also for thermal and electrical stress operations such as power cycling test. In this paper, we report the reliability results of direct copper plated interconnects through prototyping, energization test, and power cycling tests.